1. Field of the Invention
This invention relates to clock circuits employed to synchronize operations in high speed mainframe computers. More particularly, the present invention relates to on-chip phase clock generators that are synchronized and phase controlled by an off-chip master clock control to provide a synchronized processor system having replaceable synchronized unit cards.
2. Description of the Prior Art
It is well known that mainframe central processing units (CPU's) have been designed to be flexibly expanded and to operate in a distributed processing manner so that the system requires a master clock to coordinate phase synchronization of the different elements of the processor. Heretofore, one or more master clocks have been provided in different CPU's and/or different cabinets of a mainframe CPU. The clock rate and cycle rate of high speed mainframe computers has become so fast that the cable and path delays exceed the time duration of the clock pulses If the mainframe CPU requires high power clock drivers, it has been suggested that individual drivers be provided at each CPU or cabinet and that the input signals to the drivers be synchronized to a master clock located at one of the CPU's or cabinets.
Prior art mainframe computers have employed slave clock systems controlled by master clock systems. When the slave and master clock systems each employ cascading flip-flops to generate clock phases it has been possible to generate phase clock signals having separation or overlap due to process variation in the manufacture of the semi-conductors used for the flip-flops.
This latter problem has been recognized and solved by providing multi-phase output generators and clock systems at each CPU which are synchronized by cascading sync output signals. In this type system a master oscillator is provided to synchronize the multi-phase clock generators at the clock systems of the individual CPU's Such a system is shown and described in co-pending Application Ser. No. 233,396 entitled A Multiple Frequency Clock System, filed 18 Aug. 1988 and assigned to the assignee of the present invention.
While this latter type clock systems solves most of the clock problems of the prior art high speed main frame computers, the clocks are external to the high speed logic of the CPU and the clock signals supplied to the CPU are subject to delays and skew after leaving the output lines of the clock generator which cannot be further adjusted without making custom adjustment in the output lines of the clock generator.
It would be extremely desirable to provide a simplified clock system which does not require custom adjustment at the phase clock generator level and would permit interchangeability of unit cards in a CPU without clock adjustment or custom synchronization. Further, it would be desirable that the unit cards of the CPU be presynchronized at the factory production level to eliminate overlap, separation, skew and differential delay of clock pulses down to the on-chip logic level.